1. Field of the Invention
The present invention relates to a printed-wiring substrate on which an integrated-circuit element is mounted, and to a method for fabricating the printed-wiring substrate.
2. Description of the Related Art
Conventionally, in a printed-wiring substrate on which an integrated-circuit element (hereinafter referred to as an “IC chip”) is mounted, a capacitor element is provided in order to reduce switching noise of the IC chip and stabilize operation power voltage. However, when the length of wiring between the IC chip and the capacitor element provided on the printed-wiring substrate increases, the inductance of the wiring increases, so that it becomes difficult to attain the above-described object to a sufficient extent. Therefore, the capacitor element is desirably provided in the vicinity of the IC chip.
In view of the foregoing, conventionally, techniques disclosed, for example, in Japanese Patent Application Laid-Open (kokai) Nos. 7-263619 and 11-67961 have been proposed. In the technique disclosed in Japanese Patent Application Laid-Open No. 7-263619, a concave portion is formed in a base substrate (a substrate constituting the bottom portion of a multilayer printed-wiring substrate), a capacitor element is placed in the concave portion, and other layers are formed over the capacitor element to thereby embed the capacitor element within the printed-wiring substrate. In the technique disclosed in Japanese Patent Application Laid-Open No. 11-67961, a capacitor element is mounted on the surface of a core substrate (a substrate serving as a center substrate of a multilayer printed-wiring substrate), and insulating and conductor layers are stacked thereon by a buildup process to thereby constitute a multilayer printed-wiring containing a capacitor element. When a capacitor element is built into a printed-wiring substrate as described above, the length of wiring between an IC chip and the capacitor element can be shortened as compared with the case in which the capacitor element is mounted on the surface of the printed-wiring substrate. Therefore, these techniques are advantageous in that they reduce switching noise and stabilize operation power voltage.
3. Problems Solved by the Invention
The technique disclosed in Japanese Patent Application Laid-Open No. 7-263619 is preferable, because it enables a capacitor element to be built into a substrate while suppressing an increase in thickness of the substrate. However, since a concave accommodation portion must be formed in the substrate, the number of fabrication steps and the fabrication time increase, with a resultant increase in production cost.
The method disclosed in Japanese Patent Application Laid-Open No. 11-67961 does not require advance formation of a concave portion. In this method, a capacitor element is disposed in an insulating layer stacked on the core substrate. However, stacking an insulating layer by means of a buildup process is not easy, because a capacitor element of a few hundreds of nF which is actually required for achieving the above-described action has a thickness of 500 μm or greater, whereas the thickness of a typical insulating layer stacked by the buildup process has a thickness of a few tens of μm. In addition, if embedding of the capacitor element fails, a large number of process steps which had been performed before the capacitor element was built in (e.g., a step of molding the core substrate, and a step of forming conductor patterns) become useless, thereby increasing production cost.